An element of asymmetry in symmetric multiprocessor (SMP) systems is introduced by the need to select a single processor to bootstrap the system. At system start-up and whenever the system is reset, each processor in an SMP system typically is responsible for determining that its internal components and interfaces are functioning properly. The bootstrap processor (BSP) is unique in that it handles initialization procedures for the system as a whole. These procedures include checking the integrity of memory, identifying properties of the system logic, loading the operating system into memory, and starting the remaining processors. These functions temporarily introduce asymmetry into SMP systems by assigning a unique role to the BSP.
Conventional systems employ a variety of techniques for selecting a BSP from among the processors of an SMP system. In one SMP system, the processors are coupled through a dedicated interprocessor interrupt bus. On reset, each processor asserts an inverted form of an assigned processor identification number (processor ID) onto a shared line of the interrupt bus. As soon as a processor asserting a one on the line detects that another processor is asserting a zero, the first processor relinquishes the line. The processor that survives this arbitration procedure is the processor having the highest valued processor ID. This processor gains control of the bus and sends a message to all processors on the interrupt bus, identifying itself as the BSP. This approach is exemplified by SMP systems based on the Pentium Pro (registered Trademark) microprocessor of Intel Corporation.
A number of disadvantages exist in this approach to BSP selection. This BSP selection process requires a dedicated interprocessor bus. This bus is relatively slow by the standards of today's processor speeds, making the boot process unnecessarily slow. In addition, each bus can only support clusters of up to four processors. Additional processors must be accommodated in separate clusters. The need for a dedicated interprocessor bus increases the difficultly in extending this method across multiple clusters.
Another method for selecting the BSP simply designates the processor in a specified slot as the BSP. This strategy introduces a permanent asymmetry into the SMP system, and if the processor in the designated slot fails, no mechanism is provided for designating a different processor as the BSP. Thus, this BSP selection system suffers from the disadvantage of not having a fault tolerant mechanism. The fault tolerant mechanism allows the substitution of a separate processor to be the BSP if the predetermined BSP turns out to be faulty.
Other methods for selecting BSPs in SMP systems identify the first processor to write to a shared variable as the BSP. In these systems, a race occurs between all of the eligible processors. The processor with the fastest initialization time is typically elected to be the BSP. Once a BSP has been initially determined for a particular set of processors that particular processor remains the BSP unless something happens to change the initialization time of a processor in that set of processors. Vendors tend to base decisions and assumptions using this particular processor as being the BSP. However, both later versions of a processor, such as version 2 or version 3, and later versions of micro code associated with a processor can significantly affect the initialization time of a particular processor. Thus, if any processor in the system under goes such a change, due to maintenance, replacing a defective component, upgrading to a newer version to take advantage of a new capability, etc, then the race may create a new BSP. However, after the time that the vendors have based their assumptions on a particular processor being the BSP, then having an unpredictable BSP process is not beneficial. A further disadvantage is that more system components must be initialized before the BSP may be determined. These systems must initialize components outside the processors themselves, such as a shared variable in the chipset, to determine the BSP.
While the invention is subject to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and will herein be described in detail. The invention should be understood to not be limited to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.